The progress of technology provides the possibility of using powerful Digital Signal Processors (DSP) in modern telecommunication equipments. Particularly, such processors permit the design of DCE's and modems which allow multiple operating configurations. European Patent application number 91480025 entitled "DCE and Method for Processing Data Received in a DCE Allowing Multiple Operating Configurations", having a priority date of Feb. 21, 1991, and assigned to the assignee of the present application is incorporated by reference in this application. This document discloses the combination of a DSP performing the signal processing and a control processor which is used for handling the protocols. In such a DCE, the analog signal which is received from the telecommunication line is converted by means of an A/D converter, such as a sigma-delta coder, for instance. The DSP processes the train of sigma-delta pulses and derives a sequence of Pulse Coded Modulation (PCM) words. PCM words are then digitally processed in accordance with a given demodulation algorithm and the DSP derives the train of data bits which has been transmitted on the telecommunication line. For this train of bits, the DSP has to derive the corresponding characters in accordance with the considered transmission protocol. In case of High Data Link Control (HDLC) or SDLC procedures, it is required to provide the flag detection, the zero delete functions, etc . . . , well known in the telecommunication field.
Specialized components, known as HDLC or SDLC adapters, provide management of HDLC procedures. These specialized components entail some drawbacks. First they use a serial architecture and are required to operate at the bit clock rate. This obviously results in the system being limited to the speed of the serial logic technology. Secondly, since they operate on a serial train of bits, they appear to be not adapted to the architecture such as described in the above mentioned document. In such an architecture, the sigma-delta pulses are directly stored in RAM storage associated with the DSP. Signal processing is then performed on a parallel basis and the DSP computes the train of bits which is also stored in RAM. It therefore appears that the serial train of bits has no physical counterpart in the DCE and that the use of a traditional serial HDLC adapter would require the artificial generation of the train of data bits. Such generation would inevitably entail an increase in the complexity and the final cost of the DCE. Thirdly, the known HDLC adapters cannot be easily multiplexed and it is necessary to use as many adapters as there are telecommunication lines.
The possibility of performing parallel processing of the bits in order to provide HDLC procedure management functions has already been contemplated, particularly in EP application 0 346 555 entitled "Parallel Processing Method and Device for Receiving and Transmitting HDLC/SDLC Bit Streams", and IBM Technical Disclosure Bulletin vol. 32, no. 6B, November 1989, page 31, "Parallel Architecture for High Speed Bit Stuffing and Byte Alignment". The solutions which are described in the above two documents have the drawback of requiring a great number of hardware components and are not well adapted for multiplexed telecommunication lines.